1. Technical Field
The present invention generally relates to a nonvolatile ferroelectric memory device, and more specifically, to a method of obtaining high-speed operations of a nonvolatile ferroelectric memory device with a NOR type cell array using a nano scale Double Gate Cell.
2. Description of the Related Art
FIG. 1 is a cross-sectional diagram illustrating a memory cell of a conventional nonvolatile ferroelectric memory device.
Referring to FIG. 1, a memory cell of the nonvolatile ferroelectric memory device comprises an N-type drain region 4 and a N-type source region 6 which are formed in a p-type substrate 2, and also a ferroelectric layer 8 and a gate word line 10 which are sequentially formed over a channel region.
The above-described conventional nonvolatile ferroelectric memory device writes data by changing polarization of the ferroelectric layer 8, thereby changing a channel resistance, and reads data by measuring the channel resistance. More particularly, when the polarity of the ferroelectric layer 8 induces positive charges to a channel, the channel region has a high resistance. On the other hand, when the polarity of the ferroelectric layer 8 induces negative charges to a channel, the channel region has a low resistance.
However, when the size of the memory cell of the conventional nonvolatile ferroelectric memory device is scaled down, a retention characteristic degrades.
Specifically, in the nonvolatile ferroelectric memory cell having a nano scale level, the retention characteristic becomes weak even by a low voltage stress so that a voltage required to read the memory cell cannot be applied to a word line.
Conventional ferroelectric memory devices have NAND type cell arrays. When a write voltage is applied to an unselected cell in a write mode, data of unselected cells may be destroyed. As a result, it is difficult to perform a random access operation.